1. Technical Field
The present invention relates to software tools in general, and, in particular, to a method within a software tool for verifying integrated circuit designs. Still more particularly, the present invention relates to a method within a software tool for placing electrostatic discharge clamps in integrated circuit devices.
2. Description of Related Art
An electrostatic discharge (ESD) event is defined as a transfer of charges between bodies of different electrostatic potentials in proximity or via direct contact. ESD poses a reliability concern for integrated circuit devices. Different models, such as human body model (HBM), machine model (MM) and charged device model (CDM), have been used for testing integrated circuit devices to make sure the integrated circuit devices are adequately protected against an ESD event. The difference among various models mainly lies in the amount of current delivered to an integrated circuit device to emulate an ESD event encountered by the integrated circuit device.
From a circuit design standpoint, ESD clamps are typically utilized to protect an integrated circuit device against an ESD event. An ESD clamp is effectively a large switch that is normally turned off except in the presence of an ESD event. During an ESD event, the switch is turned on to produce a conductive path for charges to be drained into a grounded network within the integrated circuit device.
Generally speaking, it is imperative to minimize the number of ESD clamps placed within an integrated circuit device without compromising ESD protection because the addition of ESD clamps is expensive due to their large sizes and the blockage they cause. As such, the present disclosure targets the problem of placing ESD clamps in an integrated circuit design such that the effective resistance from every ESD-susceptible circuit to the ESD clamps meets the resistance requirements as specified by technology developers.